The present invention generally relates to an adder control method and a circuit thereof. More specifically, the present invention is directed to a control method for an adder circuit constructed of a calculator employed in a computer, and also to a circuit thereof to which the present invention is suitably applied.
A conventional adder circuit and control method thereof, is described in detailed in "Computer Architecture and Organization" by J. P. Hayes, in 1978, published by McGraw-Hill Inc. on pages 171 to 178.
In accordance with the above-described prior art, the adder circuit is realized by employing a ripple carry adder as a basic construction. An n-bit ripple carry adder is arranged by series-connecting n adders with respect to input/output lines for a carry (which will be called "a carry chain"). Each of the full adders supplies a carry bit to an adjacent full adder. When a full adder receives a carry bit from its adjoining full adder then it can output a value of its carry bit and a result bit from its two bits 2-input data and its received carry bits.
Such a condition that the carry bit is sequentially supplied and received from LSB (least Significant Bit) to MSB (Most Significant Bit) in the carry chain is referred to as "a carry propagation". A time period required for performing an n-bit addition with employment of this adder is determined by: EQU "nd",
where "d" is the propagation delay of one full adder, i.e., the time period required in the slowest full adder from the time of receipt of the rele.ant bit and the value of the carry bit based upon the relevant bit of the 2-input data and the received carry bit until the time of output of the carry bit to the adjacent full adder.
In the conventional technique, the system clock is set in such a manner that the process of this adder is completed within 1 clock cycle. As a consequence, the time period of the system clock for controlling the computer system including this adder must be selected to be longer than "nd".
Furthermore, there is a carry-lookahead adder to implement a high-speed process in an adder by reducing a time delay associated with carry bit propagation. This carry-lookahead adder does not add two inputs X and Y for every 1 bit, but produces a result Z as follows. That is to say, the two inputs X and Y are divided into a plurality of portions constructed of X(i) and Y(i); X(i), Y(i) and C(i-1) are inputted every m bits; addition operations are successively performed so as to produce a result Z(i) and carry bit C(i), whereby the result Z is produced.
The above-described prior art has such a problem that no care is taken to bit widths of the data and address in the computer systems being expanded from 32 bits to 48 bits, 64 bits or more higher bits. Then, when the bit widths are further expanded, the length of the carry chain of the adder is extended and accordingly and also the time period of the system clock for controlling the computer system is extended.
Even when the above-described carry-lookahead adder is employed to solve this conventional problem, the carry chain is expanded under such a condition that both the number of bits of the data and address are increased. Moreover, it makes the entire circuit complex to increase the number of carry-lookahead bits, so that there is a critical path in the adder circuit, therefore this look ahead solution cannot essentially solve the above-described problem of a ripple carry.
Furthermore, the above-described prior art has another problem as follows. That is, no care is taken to the chacteristics of the program such that there are many cases where one of two input data to be added with each other is a value capable of being indicated by a less bit number. In most addition processes, the value of the result has been defined in the middle of 1 clock cycle, and therefore the addition process by the computer system consumes useless time.